1. Field of the Invention
The present invention relates to a solid-state imaging device.
2. Description of the Related Art
Solid-state imaging devices, for example, X-Y addressing solid-state imaging devices typified by complementary metal-oxide semiconductor (CMOS) image sensors, each adopt a structure having noise reduction means, for example, a correlated double sampling (CDS) circuit provided for every pixel column in a pixel array area in order to reduce a fixed pattern noise due to variations in the threshold voltage of transistors in each pixel. The CDS circuit sequentially receives a reset level and a signal level output from each pixel in a selected pixel column in the pixel array area and reduces the fixed pattern noise for every pixel by determining the difference between the reset level and the signal level.
FIG. 7 is a circuit diagram showing a configuration example of a CDS circuit. Referring to FIG. 7, the CDS circuit has a structure having two capacitors 101 and 102, a sampling transistor 103, and a clamp transistor 104. One CDS circuit is provided for every vertical signal line 105 through which a signal of each pixel is transmitted. The vertical signal line 105 is wired for every vertical pixel column of a pixel array area 100 in which pixels are two-dimensionally arranged. In this example, N-channel metal oxide semiconductor (MOS) transistors are used as the sampling transistor 103 and the clamp transistor 104.
One end of the capacitor 101 is connected to the vertical signal line 105. The drain of the sampling transistor 103 is connected to the other end of the capacitor 101. A sampling pulse φSP is applied to the gate of the sampling transistor 103 through a control line 106. One end of the capacitor 102 is connected to the source of the sampling transistor 103 and the other end thereof is grounded. The source of the clamp transistor 104 is connected to the source of the sampling transistor 103. A predetermined clamp voltage Vclp is applied to the drain of the clamp transistor 104 and a clamp pulse φCLP is applied to the gate thereof through a control line 107. A connecting node among the source of the sampling transistor 103, one end of the capacitor 102, and the source of the clamp transistor 104 is hereinafter referred to as a node N.
The CDS circuit having the configuration described above has one horizontal selection transistor 108. The drain of the horizontal selection transistor 108 is connected to the node N and the source thereof is connected to a horizontal signal line 109. Horizontal selection pulses φH, which are sequentially output from a horizontal scanning circuit 110 in synchronization with horizontal scanning, are applied to the gate of the horizontal selection transistor 108. Applying a horizontal scanning pulse φH to the gate of the horizontal selection transistor 108 turns on the horizontal selection transistor 108 so as to output the voltage at the node N to the horizontal signal line 109.
The circuit operation of the CDS circuit having the configuration described above will now be described. First, with a pixel being reset, the sampling transistor 103 and the clamp transistor 104 are turned on and the horizontal selection transistor 108 is turned off to charge the capacitors 101 and 102 based on a reset voltage Vrst of the pixel output through the vertical signal line 105. Electric charges Q1 and Q2 that are calculated according to the following equations are stored in the capacitors 101 and 102:Q1=C1 (Vrst−Vclp)Q2=C2×Vclp  [Formula 1]where C1 and C1 represent the capacitances of the capacitors 101 and 102, respectively.
After the clamp transistor 104 is turned off, a signal charge is read out from a photoelectric transducer in the pixel. A signal voltage Vsig of the pixel is output through the vertical signal line 105 to vary a voltage Vout at the node N according to the following equation:Vout=Vclp+C1 (Vsig−Vrst)/(C1+C2)  [Formula 2]Accordingly, even if the transistors of the pixel vary in threshold value, a fixed pattern noise can be reduced based on (Vsig−Vrst).
It is assumed that one CDS circuit is provided for every vertical signal line 105 in the above description. In contrast, solid-state imaging devices each having a structure in which multiple, for example, two CDS circuits are provided for every vertical signal line 105 have been proposed in recent years in order to expand the dynamic range of optical detection (for example, Japanese Unexamined Patent Application Publication No. 2003-87665). With a structure in which multiple CDS circuits are provided for every vertical signal line 105, it is possible to increase the frame rate by, for example, reading out the signals of pixels in multiple pixel rows during one horizontal blanking period and outputting in parallel the readout signals of the pixels in the multiple pixel rows.
However, the provision of multiple CDS circuits for every vertical signal line 105 increases the area occupied by a circuit area around a pixel array area including the CDS circuits. Accordingly, the semiconductor chip (semiconductor substrate) on which the pixel array area and the peripheral circuits are integrated is increased in size and applications to which the solid-state imaging devices can be mounted are limited. Particularly, in order to improve the effect of noise reduction, the capacitors 101 and 102 must have large capacitances. Increasing the capacitances of the capacitors 101 and 102 increases the areas occupied by the capacitors 101 and 102, thus further increasing the size of the semiconductor chip.
When, for example, two CDS circuits are provided for every vertical signal line 105, the two CDS circuits cannot be arranged in the lateral direction and, therefore, they must be arranged in the vertical direction under such present circumstances because the pixel pitch has become very small along with an increase in the number of pixels in the solid-state imaging device in recent years and sufficient space cannot be allocated to the CDS circuits in the lateral direction (horizontal direction). Hence, it is necessary to slenderize the shape of the two capacitors 101 and 102 provided for every CDS circuit and to arrange the capacitors 101 and 102 in sequence along the wiring direction of the vertical signal line 105 under the restriction that the pixel pitch becomes smaller along with an increase in the number of pixels and sufficient space cannot be allocated to the CDS circuits in the lateral direction, thereby increasing the size of the semiconductor chip particularly in the vertical direction.